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11. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51? instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 28), and interfaces directly with the ana-
log and digital subsystems providing a complete data acquisition or control-system solution in a single inte-
grated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 11.1 for a block diagram).
The CIP-51 includes the following features:
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?
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Fully Compatible with MCS-51 Instruction Set
48 MIPS Peak Throughput with 48 MHz Clock
0 to 48 MHz Clock Frequency
Extended Interrupt Handler
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Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
DATA BUS
ACCUMULATOR
TMP1
TMP2
B REGISTER
STACK POINTER
PSW
ALU
SRAM
ADDRESS
REGISTER
SRAM
DATA BUS
SFR_ADDRESS
BUFFER
D8
SFR
SFR_CONTROL
DATA POINTER
D8
D8
BUS
INTERFACE
SFR_WRITE_DATA
SFR_READ_DATA
PC INCREMENTER
PROGRAM COUNTER (PC)
D8
MEM_ADDRESS
MEM_CONTROL
PRGM. ADDRESS REG.
A16
MEMORY
INTERFACE
MEM_WRITE_DATA
MEM_READ_DATA
PIPELINE
D8
RESET
CLOCK
STOP
IDLE
CONTROL
LOGIC
POWER CONTROL
REGISTER
D8
D8
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
Figure 11.1. CIP-51 Block Diagram
Rev. 1.4
79
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